1. Field of the Invention
The present invention relates to on-chip termination impedance control, and more particularly, to techniques for providing greater flexibility with respect to on-chip termination impedance control on an integrated circuit.
2. Description of the Related Art
Signal reflection can occur on transmission lines when there is a mismatch between the impedance of the transmission line and the impedance of the transmitter and/or receiver. The reflected signal can interfere with the transmitted signal, causing distortion and degrading signal integrity.
To solve this problem, transmission lines are resistively terminated by a matching impedance to minimize or eliminate signal reflection. Input/output (IO) pins on an integrated circuit package are often terminated by coupling external termination resistors to the appropriate IO pins. However, many integrated circuit packages require a large number of termination resistors, because they have a large number of IO pins. Therefore, it is becoming more common to resistively terminate transmission lines using on-chip termination (OCT) to reduce the number of external components.
The Stratix® II field programmable gate array (FPGA) made by Altera, Corporation of San Jose, Calif. has calibrated on-chip termination to support a wide range of high-speed memory interfaces in a single device. Because different memory interfaces require different power supply voltages, input/output (IO) buffers are arranged in input/output (IO) banks in order to support memory interfaces flexibly. Each bank has its own power supply independent of other IO banks. IO buffers within the same IO bank share the same power supply. Calibrated on-chip source termination (Rs) and parallel termination (Rt) are supported in top and bottom IO banks to achieve higher memory interface performance. But the side IO banks on the FPGA do not support calibrated source and parallel on-chip termination. As a result, the side IO banks can only support lower performance memory interfaces.
Therefore, it would be desirable to provide increased flexibility on an FPGA by allowing more of the IO banks to support high speed memory interfaces.